1. Field of the Invention
The present invention relates to a multiplying circuit, and more particularly, to a binary multiplier formed of an integrated circuit.
2. Description of the Related Art
In a conventional binary multiplier, or n bits.times.n bits multiplying circuit formed using an integrated circuit, a multiplication operation is carried out such that, all bits of a multiplicand are multiplied one by one by each single bit of the multiplier to make logical products so as to form n-sets of n-bit partial products, and the thus obtained partial products are summed up using full adders. Such a multiplying circuit is called "array type multiplier".
FIG. 1 is a block diagram showing one example of a conventional multiplying circuit. The conventional multiplying circuit shown in FIG. 1, is an array type multiplier of 4 bits.times.4 bits, including sixteen AND gates A1 to A16, and four full adder series FA1 to FA4; FA5 to FA8; FA9 to FA12; and FA13 to FA16. First of all, multiplication of each bit of multiplicand X1 to X4 and each bit of multiplier Y1 to Y4 is executed in a corresponding AND gate of A1 to A16, to make a respective logical product The outputs of the AND gates A1 to A4 for forming a first set of logical products are input into respective first full adders FA1 to FA4. Despite that the first full adders FA1 to FA4 do not make any actual adding operation, they are provided so that the regularity of the layout for interconnecting will not be lost. These outputs of the first full adders FA1 to FA4 are added in second full adders FA5 to FA8 to the respective outputs of the AND gates A5 to A8 for forming second set of logical products. Then, the outputs of the second full adders FA5 to FA8 are added in third full adders FA9 to FA12 to the respective outputs of the AND gates A9 to A12 for forming a third set of logical products. Finally, the outputs of the third full adders FA9 to FA12 are added in fourth full adders FA13 to FA16 to the respective outputs of the AND gates A13 to A16 for forming a fourth set of logical products, whereby multiplication result P1 to P8 can be obtained. Here, the lowest three bits P1 to P3 in the multiplication result are outputted directly from the first to third full adder series, respectively.
The maximum delay path of the multiplying circuit is composed of one step for all the AND gates and seven steps for full adders. When a larger multiplying device of n bits.times.n bits is constructed applying the above multiplying circuit structure, the maximum delay path includes one step for all AND gate and (2n-1) steps for full adders, or is approximately proportional to n.
Since the above-stated conventional array type multiplying circuit is composed of simple macro-cells arranged regularly, it is easy to design but has a drawback that the operation speed is low. The delay time for this multiplying circuit is proportional to n or the bit number of the multiplicand and multiplier. so that the circumstance becomes more unfavorable particularly when the circuit is required to be large-sized. On the other hand, since the total number of AND gates and full adders in the multiplying device of n bits.times.n bits is in proportion with square of n, this disadvantageously increases the chip in size.